- 35万-45万/年
- 上海
- |
- 5年以上
- |
- 硕士
- |
- 全职
职位诱惑: 五险一金,年底双薪,天天下午茶,年度旅游,技术领先,成长空间大,节日礼物
发布时间: 2019-03-29发布
职位描述
RESPONSIBILITIES:
1. Develop the specification & implement the circuit for the DDR blocks.
2. Design DDR/DDR2/DDR3 memory PHY both for receiver and transmitter.
3. Interact with the layout team and guide the critical layout area.
4. Support test & product team with chip debugging.
5. Assist systems team for board design & debug.
6. Inateract with chip atchitecture and study industry standards to understand system requirements and perform feasibility study of new product proposals.
EDUCATION/SKILLS:
1. BSEE/MSEE with Minimum 5-year experience in DDR design.
2. Well understand DDR/DDR2/DDR3 protocal.
3. Experience with analog simulation environment and schematic simulation.
4. Good English communication skill is required.
5. Experienced with FPGA is a plus.
6. Self-motivated and a strong team player.
职位发布者
Gloria Tang
HR
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