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英伟达半导体科技上海有限公司

IC设计工程师 ASIC Design Engineer (Clock)

  • 20万-40万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 福利好,成长空间大,技术领先,免费班车

发布时间: 2018-06-29发布

职位描述

The NVIDIA SOC Clock group is now looking for ASIC engineers with strong logic design background.  In this position, you will take part in all stages to design modern complex GPU chips with state-of-art features and flows. To implement various functions, you will work directly with different global teams, as ARCH/SW, ASIC Design, CAD, Package, DFT and Physical Design teams. Additionally, you will be involved in defining and creating methodologies that create more efficient and flexible SOCs in future.

What you'll be doing
·         Chip top integration and assembling, design quality checks
·         Module-level or Chip-level logic design, synthesis, timing constraints
·         Chip-level validation, both for function and test mode
·         Methodology or Flow development for above tasks.
 
What we need to see
·         BS / MS in electrical / computer engineering and related.
·         Understand ASIC design and implementation flow
·         Familiar with design/verification languages as Verilog/VHDL, C/C++
·         Know industrial standard scripting language as Perl or Python
 
Ways to stand out from the crowd
·         Excellent analytical and problem-solving skills
·         Fluent English and excellent communication skills
·         Good team work spirit, easy to cooperate with team members
·         Experience in RTL build and design automation is a plus
·         Understand JTAG or DFT is a plus
 

职位发布者

Heather

HR

7天

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