Verification Application Engineer (Formal)

Position Description
Provides technical expertise, support, and guidance of formal verification tools and effective application of formal verification within client’s methodology and flows. Includes analysis of environment and setup, identification of appropriate blocks and metrics, analysis of tool performance and problem complexity, and optimizing modeling logic, formal testbenches and environment for optimal tool performance. May be involved in defining, scoping and implementing detailed customer verification requirements.
Will work closely with R&D to specify and develop next generation features, capabilities and applications. Ensures that client’s needs have been met and that the product/solution is fully functioning according to specification.
Will be the formal verification champion and provide training on concepts, methodology and tool usage. Application of formal methods including formal property verification, sequential equivalence checking, formal coverage analysis, connectivity checking and other formal verification apps.
Requirement:
Requires a minimum of 5 years of related experience. Possesses a solid understanding of Formal Verification concepts plus hands-on experience verifying and signing-off using formal verification.
Exercises independent judgment in selecting methods and techniques to obtain solutions..
 
Skills & Education Required
Bachelor degree in Electrical Engineering. Masters or Ph.D. degree preferred.
8years of experience in design and verification of digital designs.
5years of work experience in formal and functional verification.
 
Experience with formal verification tools: VC Formal, Jasper, Questa Formal, OneSpin,
Understand of Formal Applications:
- Formal Property Verification
- Sequential Equivalence Checking
- Formal Coverage Analysis
- Formal Connectivity Checking