Senior Verification Engineer

Job Responsibility:

• IP Verification including developing testbench, writing test plan & test case, regressions, coverage and infrastructure development.
• Apply necessary verification methodologies such as UVM, power aware simulation, formal, etc to achieve the verification goals.

• MSEE from new graduate to 10 years DV experience for Junior/Senior title.
• Good knowledge of Verilog/SystemVerilog/UVM or VMM and work in Linux platforms.
• Be skillful in perl/ruby script programming is better.
• A solid foundation of Computer Architecture and Operating system
• Have complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (any of PCI-e, AXI, AMBA) .
• Good communicate in oral and documentation.
• Good English hearing, speaking, reading and writing capabilities.
• Good at learning new technology by self. Has strong interesting on technical.