Principal Design Engineer, Serdes R&D
Responsible for design, layout, verification, and characterization of high-speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers, high-speed CML, and other SerDes/CDR/PLL building blocks at data rates of 25Gb/s and higher.
You will work as a part of a Serdes team in a dynamic startup environment, taking an active role in design implementation, design reviews, contributing to product definition, proposing and evaluating technical solutions, writing design specifications and test requirement documents, etc. The ideal candidate is a hands-on self-starter who is able to develop design based on design specification and schedule.
· 10+ years’ experience for Bachelor in Electrical Engineering or 7+ years’ experience for M.S in Electrical Engineering.
· 5+ years of working/research experience in high-speed CMOS SerDes design (CTLEs, TIAs, PLLs, DFEs, etc.), M.S in Electrical Engineering and Ph.D. preferred
· Have experience designing in advanced CMOS (65nm or below) at data rates of at least 10Gb/s and/or RF circuits operating at 5GHz or above
· Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
· Good understanding of high-speed layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
· Working knowledge of theoretical and practical aspects of electro-magnetic structures including transmission lines, spiral inductors, resonant circuits, etc. (HFSS experience is a plus)
· Experience with precision analog and mixed-signal circuits is a plus
· Able to assume responsibility for a variety of technical tasks and to work independently
· Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
· Good communication
· Familiar with USB, MIPI, HDMI, DP, PCIe, 10GKR, CCIX and other standard.