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Cadence

Lead Design Engineer, Serdes R&D

  • 18万-30万/年
  • 南京
  • |
  • 3年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 技术领先,成长空间大

发布时间: 2019-01-17发布

职位描述


Job description
Responsible for design, layout, verification, and characterization of high-speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers, high-speed CML, and other SerDes/CDR/PLL building blocks at data rates of 25Gb/s and higher.
You will work as a part of a Serdes team in a dynamic startup environment, taking an active role in design implementation, design reviews, contributing to product definition, proposing and evaluating technical solutions, writing design specificaons and test requirement documents, etc.
You are expected to develop the design according to the design specification, provide your input and feedback to the design specification according to your own experience and work with other team member together to achieve the performance and schedule requirement of the product.
DESIRED QUALIFICATIONS
·        6+ years’ experience for Bachelor in Electrical Engineering or 3+ years’ experience for M.S in Electrical Engineering.
·        Working/research experience in high-speed CMOS SerDes design (CTLEs, TIAs, PLLs, DFEs, etc.),
·        Nice to have experience designing in advanced CMOS (65nm or below) at data rates of at least 10Gb/s and/or RF circuits operating at 5GHz or above
·        Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
·        Good understanding of high-speed layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
·        Working knowledge of theoretical and practical aspects of electro-magnetic structures including transmission lines, spiral inductors, resonant circuits, etc.
·        Experience with precision analog and mixed-signal circuits is a plus
·        Able to assume responsibility for a variety of technical tasks and to work independently
·        Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs. Good communication
·        Familiar with USB,MIPI, HDMI, DP, PCIe, 10GKR, CCIX and other standard.
 

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

99%

简历及时处理率