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Cadence

Analog IC Design Engineer (Serdes)_Nanjing

收藏职位
  • 我要分享
  • 30万-50万/年
  • 南京
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 成长空间大,技术领先

发布时间: 2019-04-17发布

职位描述

Responsible for design, layout, verification, and characterization of high-speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers, high-speed CML, and other SERDES/CDR/PLL building blocks at data rates of 25Gb/s and higher.
You will work as a part of a SERDES team in a dynamic startup environment, taking an active role in design implementation, design reviews, contributing to product definition, proposing and evaluating technical solutions, writing design specifications and test requirement documents, etc.
 You are expected to develop the design according to the design specification, provide your input and feedback to the design specification according to your own experience and work with other team member together to achieve the performance and schedule requirement of the product. You are expected to learn the new technology proactively and grow with the team to be the world leading engineer in SERDES design.
DESIRED QUALIFICATIONS
·        3+ years’ experience for Bachelor in Electrical Engineering or M.S in Electrical Engineering.
·        Candidate should have working knowledge of a set of common SerDes standards and their electrical requirements, and a thorough understanding of jitter.
·        Nice to have experience designing in advanced CMOS at data rates of at least 10Gb/s and/or RF circuits operating at 5GHz or above
·        Proficient with Cadence EDA tool set
·        Good understanding of high-speed layout considerations
·        Experience with precision analog and mixed-signal circuits is a plus
·        Proactive quick learner and good communication skill
·        Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
 

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

93%

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