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哎呀,这个职位已经下线啦
Cadence

软件研发实习生-数模混合仿真器

  • 5万-8万/年
  • 北京
  • |
  • 应届生/在校生
  • |
  • 硕士
  • |
  • 实习

职位诱惑: 老板nice,天天下午茶,技术领先,成长空间大,节日礼物,技能培训,转正机会

发布时间: 2020-03-04发布

职位描述

Position Description:
Develop, enhance and maintain digital mixed signal simulator which supports the co-sim between different HDL languages, such as Verilog, VHDL, SystemVerilog, etc, with some direction from manager or senior engineers
Position Requirements:
1. Familiar with Verilog, VHDL, SystemVerilog language
2. Analog circuit or digital simulator development experiences
3. Skilled in C/C++ programming, familiar with development under Linux/Unix environment.
4. Being familiar with Real number modeling is a plus
5. Being familiar with Digital Mixed-signal design is a plus
6. Being familiar with low power design is a plus

要求:每周工作4天以上,持续至少6个月以上,硕士相关专业2019年及以后毕业

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

97%

简历及时处理率