哎呀,这个职位已经下线啦
Cadence
软件研发实习生-Verilog-A Simulator
- 5万-8万/年
- 北京
- |
- 应届生/在校生
- |
- 硕士
- |
- 实习
职位诱惑: 老板nice,天天下午茶,年度旅游,技术领先,成长空间大,节日礼物,技能培训,转正机会
发布时间: 2020-03-04发布
职位描述
Position Description:
Develop, enhance and maintain Verilog-A simulator.
Position Requirements:
1. Familiar with Spice, Verilog-A, Verilog-AMS language
2. Skilled in C++ programming, familiar with development under Linux/Unix environment.
3. Analog circuit or digital simulator development experiences is a plus
4. EE or CS Master degree with related working experience
要求:每周工作4天以上,持续至少6个月以上,硕士相关专业2019年及以后毕业
职位发布者
cadence hr
Sr.Manager&BP
7天
简历处理用时
97%