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NVIDIA

Physical Design Engineer

收藏职位
  • 我要分享
  • 20万-40万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大

发布时间: 2018-01-10发布

职位描述

工作地点:上海 浦东新区 秋月路26号

We are now looking for an ASIC PD Engineer.
 
What you'll be doing
·        Chip integration and netlist generation
·        Synthesis
·        Netlist quality check
·        Formal Verification
·        Constraints creation and validation, timing budget.
·        Co-work with PR engineers to implement chip partition and floorplan
·        Work in conjunction with RR engineers to achieve timing closure for both partition and full chip level
·        Achieve special timing closure, such as io, test, clock etc.
·        Function eco creation
·        Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
·        Flow automation development
·        Methodology in any of above areas.

What we need to see
·        BSEE, MSEE is preferred
·        Project experience in IC design implementation
·        Courses taken in circuit design, digital design
·        Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) is preferred

·        Ways to stand out from the crowd:
·        Proficient user of Perl or TCL is preferred
·        Excellent English communication skill
 

职位发布者

Heather

HR

7天

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