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NVIDIA

Senior Design Verification Engineer

收藏职位
  • 我要分享
  • 30万-50万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大

发布时间: 2018-01-10发布

职位描述

工作地点:上海 浦东新区 秋月路26号

What you'll be doing

  • You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality state of the art products.
  • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
  • You responses to build block/IP testbench based on UVM methodology.
  • The responsibilities includes building test run and regression flow. Triage failures in regression and help designer root cause the bug.
  • Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
  • Take SOC verification on fullchip test environment for IPs
  • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
  • Deploy the advanced verification methodology and infrastructure of the SOC/IP
 
What we need to see
  • BS / MS in electrical / computer engineering and related.
  • 3+ years (MS) or 5+ years (BS) working experience.
  • Familiar with advance verification methodology (UVM, VMM, OVM, etc), tools and flow
  • Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
  • Deep understanding in Verilog and HVL (High-level Verification Language)
 
Ways to stand out from the crowd
  • Strong programming skills in Perl and C/C++is plus
  • Having good arch/design experience is big plus.
  • At least good at one of the script programing lanange : Perl, Shell, Ruby, Python, etc.
  • Fluent English (both written and spoken) and excellent communication skills
  • Proven ability to work independently as well as in a multi-disciplinary group environment
  • Strong analytical skills

职位发布者

Heather

HR

7天

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