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Cadence

Analog Layout Design Engineer (IP Group)

  • 9万-15万/年
  • 上海
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,年终奖金,年底双薪

发布时间: 2018-12-18发布

职位描述

Position Description:     
•Skillful capable of AMS layout Design area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc.
•Proficient with Cadence layout tools specifically Virtuoso XL and Assura (Cadence 6.1 experience a plus)  
•Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
•Fundamental understanding of IC design technology and process/methodology
•Skilled in Analog IC top level chip assembly including floorplanning and block layout
•Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
 
Position Requirements:
BSEE degree with 1+ years of applicable experience in analog design industry.
Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
Requires good communication skills in English and Chinese.

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

99%

简历及时处理率