Principal Application Engineer - DDR IP

      Position Description:      
Ø  Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
Ø  Interface with customer architects and IP business unit to enable evaluation of application specific IP performance and features per customer’s SoC requirements.
Ø  Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
Ø  Providing customer feedback on new/existing requirements for Design IP usage from customers to the R&D business unit
Ø  Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SoC
Ø  Writing application notes and review protocol specifications for Design IP
 
      Position Requirements:
Ø  5+ years relative working experience with M.S. Electrical/Computer Engineering (or similar degree)
Ø  Experience in SoC design
Ø  Good understanding of SoC architecture
Ø  Experience with DDR or PCIe or Ethernet or USB subsystem hardware or firmware developing, testing or debugging
Ø  Good understanding DDR or PCIe or Ethernet or USB protocols
Ø  Good written and verbal communication skills and problem solving skills are required
Ø  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
Ø  Travel within AP region may be required.
Ø  Good understanding of the semiconductor IP marketplace and ecosystem is a plus