Senior Application Engineer (Front-end Verification)
- 20万-25万/年
- 上海
- |
- 1-3年
- |
- 硕士
- |
- 全职
职位诱惑: 五险一金,年终奖金,年底双薪,股票期权
发布时间: 2018-08-08发布
职位描述
Position Description:
- Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
- Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Providing technical expertise to address clients’ queries, which need expert involvement.
- Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
Position Requirements:
- 1~2 years’ experience in the following areas:
- Design experience in Verilog/VHDL for IP or SoC chip level.
- HW verification with knowledge of System Verilog/VHDL and HDL simulators
- FPGA prototyping project experience
- Experience with hardware emulator or accelerator is a big advantage
- Advanced Verification Methodology like UVM is a plus
- Knowledge of Unix and Linux is highly desired
- Strong verbal and written communication skills in English
- Strong teamwork skills with good human relationship
职位发布者
cadence hr
Sr.Manager&BP
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,浦东嘉里城(7号线,花木路站)
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