IC模拟版图

Essential Functions:
Duties and responsibilities of this position include but are not limited to the following:
1.Create layout that passes LVS and DRC for the assigned design project in a specified process.
2.Make a floor plan with the designer.
3.Provide net list to the project leader for bonding diagram determination.
4.Closely work with designer to ensure ESD, latch up, power bus width, die size and pad placement all meet requirement.
5.Perform LVS, DRC and other necessary operations for tape out and create corresponding documents.
6.Other duties that assigned by upper supervisor.

Qualifications:
1.Majored in related microelectronic discipline；
2.More than three year CMOS IC full custom layout experience；
3.Familiar with Cadence IC layout （virtuoso） and verification tools （calibre）；熟练操作virtuoso layout + Calibre Verifications（DRC，LVS，xRC等）；
4.HV layout and successfully tape out experience；最好有HV layout经验或成功tape out过一个项目；
5.Auto P＆R or Parasitic extractions are more appreciated；最好有自动布局布线基础

该职位locates in Xiamen. 欢迎有意向到厦门长期发展的同学们联系我们：0592-3018251