Engineer/Sr. Engineer of SoC Design Verification

Responsibilities:

• Understanding the expected functionality of designs.
• Developing testing and regression plans.
• Designing and developing verification environment.
• Running RTL and gate-level simulations/regression.
• Code/functional coverage development, analysis and closure.

• Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.)
• Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…).
• Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
• Scripting and automation skills (tcl, perl, makefile etc) a plus.
• Familiar with C/C++.
• Knowledge of DDR/Video/ARM/USB/PCIE, Low Power Verification with UPF and design experience is a plus.
• Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment, and knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus.
• Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.
• Independent and self-managing.