Shanghai power team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies for power optimization. We want to hire promising talent who can handle project(s) individually/collectively and add new dimension to the team.
1. You'll be responsible for DFT planning, DFT implementation, DFT verification and silicon bring up at IP or fullchip level for all of NVIDIA's semiconductor products, starting with Memory BIST design and implementation.
2. In addition, you will have chance to improve DFT design, architecture and flow continuously.
1. BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or related domains.
2. Solid background on Verilog and ASIC design
3. Proven knowledge and expertise in defining and implementing 1500, Scan test plans and ATPG
4. Deep understanding on Memory BIST
5. Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
6. Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
7. Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
8. Strong programming and scripting skills in Perl, Python or Tcl desired
9. Excellent written and oral communication skills in English with the curiosity to work on rare challenges