FPGA Software Validation Engineer

Accountabilities:
- Understand Lattice FPGA architecture as well as competitor’s
- Well known the process flow of EDA tools for FPGA
- Well known EDA SW validation method and process
- Write test cases in Verilog/VHDL to verify key features during software development
- Software product benchmarking compared to competitor
- Responsible for new FPGA device evaluation
- Responsible for Lattice software product validation and verification
- Responsible for root cause analysis on quality of results (QoR)
- Responsible for static timing analysis (STA) on QoR benchmarking
- Responsible for synthesis tool evaluation and verification vs B35 party vendor
- Provide QA testing report and analysis report

Required Skills:
- Skill in digital logic circuits design with FPGA application
- Skill in Verilog/VHDL coding
- Familiar with FPGA technologies, preferably Lattice
- Experience in applying EDA tools such as Diamond, ISE/Vivado or QuartusII
- Experience in synthesis tools application as well as simulation tools
- Experience in script language (Python, Perl, Tcl or Shell and etc.).
- Good written and verbal communication skills in English