数字后端物理设计工程师

Job Title: Chip Level Sr Staff Engineer
 
Location: Shanghai / Beijing
 
Position Description
Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Work on physical design of deep sub-micron Server CPU chips top level (full chip) floorplanning, timing closure, place&route, physical verification etc. Especially focus on top level physical partition, block sizing and shaping, power planning, top level place & routing.
 
Responsibilities
1. Work on top level physical implementation flow from RTL to post-route, and focus on physical design part: top level physical partition, block sizing and shaping, block port assignment, power planning, top level place & routing.
2. Critical issue resolve on top congestion or timing issues. Overall view and solution made to relief congestion hot spot and fix timing.
3. Evaluate new EDA PR tools and PR methodology best-fitted for current project.
4. Evaluate new process feature based on current project, and help to figure out best top level PR flow.
5. Help block engineers to solve physical issues.
6. Better be expert on one or more aspect like: power/ clock/ PV.
 
Qualifications
Education and Experience
MSEE with 10+ years or Bachelor with 12+ years of industrial experience of deep submicron digital ASIC design
 
Skills and Knowledge
1. Good knowledge in following physical design concepts: synthesis, floorplan, place-and-route, timing closure, timing sign-off, DFT, power analysis, hierarchical flow
2. Skilled in the field of IC digital implementation flow and major EDA tools such as DC, ICC/ICC2, EDI/INNOVUS, PT, Redhawk or equivalent
3. Skilled in scripting and building flow automation using Tcl, Perl, Python or equivalent
4. Good listening, writing and speaking English, self-motivated
5. Good communication skills, strong interpersonal skills and the flexibility
6. 5+ projects tapeout experience is a good plus
7. 16nm and beyond (advanced node) tapeout experience is a good plus