关注微信 意见反馈

扫描关注摩尔人半导体招聘

摩尔人招聘
确定

您已提交成功

查看帮助中心
哎呀,这个职位已经下线啦
Cadence

Software Engineer-Virtuoso Design Environment

  • 20万-40万/年
  • 北京
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,成长空间大,技术领先,技能培训

发布时间: 2020-03-04发布

职位描述

The Position Description is…Custom digital and analog circuit designers must generate and interpret large amounts of complex simulation data. Virtuoso Analog Design Environment delivers advanced design simulation for fast and accurate verification, it designed to help users create manufacturing-robust designs, Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses. By supporting extensive exploration of multiple designs against their objective specifications, Virtuoso Analog Design Environment sets the standard in fast and accurate design verification.
As an ADE team member, you will:
* Work closely with other teams and customers in order to streamline tool flow and deliver new capabilities.
* Implement internal algorithms, provide APIs for other tools to integrate, and provide GUI support for the end user.
* Carefully consider data structures to handle large data sets.
* Demonstrate strong OO knowledge using C++.
* Write tests to validate your implementation.
* Encourage innovation by introducing and new technology into EDA area.The Position Requirements are…- Demonstrated proficiency in C++ and general software development skills 
- Master in Computer Science or Electrical Engineering required
- Good English communication skill both verbally and writing
- Good problem solving skill and team work spirit
- Familiarity with XML and/or HTML is a plus
- Experience with Cadence Virtuoso or analog circuit design is a plus

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

97%

简历及时处理率