Analog/Memory Layout Design Engineer

Job Description:
1. Responsible for learning PDK from advanced process Foundry and going through layout design flow.
2. Responsible for laying all kinds of memory/stdcell/analog IP layouts.
3. Responsible for instructing and training junior layout engineers.
4. Responsible for project plan, schedule and daily management.
5. Responsible for IP delivery and support for other teams.

Requirements:
1. Bachelor degree (or above) in Electrical Engineering or other related engineering field.
2. At least 6 years’ experience in layout design with rich tapeout experience.
4. Familiar with IC layout design flow(DRC/LVS/PEX) and EDA tools(Calibre/Hercules/Star-RC)
5. Experienced in memory and standard cell library design is a plus.
6. Experienced in FinFET process is a plus.
7. Patient, a good team player, good communication skills.
8. English language skill in writing is a must.