Feint Intern
- 2万-3万/年
- 上海
- |
- 应届生/在校生
- |
- 本科
- |
- 实习
职位诱惑: 老板nice,福利好
发布时间: 2018-08-29发布
职位描述
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for RTL design and synthesis of part of system IP
- Run front-end integration flow (synthesis, LINT, DFT, etc.), deliver netlist
s with good quality. Work with RTL owner and physical design team on timing cl
osure and report check.
- Take part in the RTL design of some system IP blocks. Learn the spec and imp
lement in RTL. Work with verification engineer on debugging.
PREFERRED EXPERIENCE:
- Master in electronics, computer, communication or relative majors.
- Skilled in Verilog RTL design.
- Experience in synthesis, timing analysis and formal verification.
- Experience in ASIC or FPGA projects.
- Familiar with front-end EDA tools and flows.
- Fluent written and verbal English.