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ADI

DV Engineer - Healthcare Team

收藏职位
  • 我要分享
  • 30万-50万/年
  • 上海
  • |
  • 3年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,股票期权,年度旅游,通讯津贴,技能培训

发布时间: 2018-09-05发布

职位描述

Team Introduction:
ADI’s Healthcare Group is focused on the state of the art photoelectric mixed signal IC development for healthcare consumer products. We are looking for a highly motivated individual to join our team and take the digital verification tasks. This is a great opportunity for someone who is ready to expand on their verification skills and contribute to a wider spectrum of digital + analog design practices.
 
Responsibility:
•             Define digital verification and mix-signal verification methodology.
•             Develop verification plan and arrange reviews meetings.
•             Build UVM based test-benches according to the verification requirements.
•             Perform chip-level integration verification as well as sub-system and module level verification.
•             Develop testcases, assertions and cover-groups that align with verification plan.
•             Driving for functional/structural coverage closure.
•             Team work with digital design engineers to execute gate level simulation.
•             Team work with analog design engineers to support CO-SIM in environment and simulation flow.
•             Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.
•             Successfully communicate with designers of multiple product types to deliver first-pass success silicon.
 
Requirement:
•             MSEE or PhD in EE or related
•             4-10 years of professional experience
•             Experience in UVM and SystemVerilog
•             Experience in mixed-signal verification is preferred
•             Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
•             Experience in scripting languages such as Perl and TCL are a plus
•             Experience in power-aware simulations and debug is a big plus
•             Experience in formal verification tools is a plus
•             Be good at English
•             Must have exceptional interpersonal and communication skills
•             Must be a self-starter, should be able to work on assignments with minimal directions
 

职位发布者

Elyn WEI

HR

7天

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