ASIC Design engineer (Image Signal Processor)

AMD Image Signal Processor (ISP) team has immediate opening of MTS ASIC design engineer. The successful candidate would be hired in as staff engineer level, with the expectation that they would have minimal 3-5 years of RTL design experience in the multimedia, image processing or similar industry. A candidate that has a strong image science background with a focus on image signal processing (ISP) is highly desirable.
 
PREFERRED EXPERIENCE:
·       BS-CS/BS-EE with at least 7 years' experience or MS with at least 5 years' experience in ASIC/SoC design
·       Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
·       Familiar with front-end EDA tools and flows.
·       Strong multimedia/video/camera related system level knowledge and experience
·       Strong individual analysis, problem solving skills and teamwork attitude
·       Will be a plus if having low power design, debugging and modeling experience
·       Will be a plus if having FPGA validation experience
·       Experience of working with multi-site teams is preferred
 
KEY RESPONSIBILITY:
·       Participate in ISP hardware architecture definition, responsible for ISP block level macro architecture
·       Design and implement ISP pipeline and blocks based on IP architecture and algorithm specification
·       Closely interact with algorithm, verification and firmware team in new feature definition, deliver design specification and program guide
·       Work with verification team and firmware team to complete ISP pipeline pre silicon and post silicon validation
·       Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency
·       Collaborate and interface with local and global management to make accountable deliverables on time