哎呀,这个职位已经下线啦
Cadence
Principal Application Engineer –数字后端设计
- 40万-55万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,老板nice,福利好,年底双薪,股票期权
发布时间: 2018-08-31发布
职位描述
Position Description:
- To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
- To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, for challenging low power designs, for 200MHz to several GHz big chips.
- Have real design experience including conformal check, logic synthesys, P&R, CTS, SSTA, MMMC to close timing, power and die area.
- Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
- To play a leading role among other team members, while receive little instruction on routine and general assignments.
Position Requirements:
- A bachelor's degree is essential and 6+ years’ experience in IC design, electronic engineering or computer science applications.
- Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
- Requires working knowledge of one or more programming languages, and effective communication and soft skills.
- An MS degree and/or working experience in multi-nation IC design house is a plus.
职位发布者
cadence hr
Sr.Manager&BP
7天
简历处理用时
97%
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,浦东嘉里城(7号线,花木路站)
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