数字后端CAD工程师 ASIC PD Methodology Engineer
Responsible for the development of timing analysis and closure methodologies and flow automation for large and high-speed semicustom chips using deep submicron processes. This includes evaluating and helping improve commercial timing signoff tools, developing internal tools and solutions, and supporting the physical design implementation team to achieve speed of light timing closure.
1. BS/MS in Electrical or Computer Engineering
2. Experience in physical design implementation of deep submicron digital ASIC.
3. Prior experience in synthesis, timing constraints, timing analysis and timing closure.
4. Power user of commercial STA tools such as Synopsys PrimeTime or Cadence ETS
5. Solid knowledge about STA and timing signoff
6. Proficiency experience in Perl, TCL, Python or C++.
7. Good communication skills
8. Flow development or automation experience in ASIC backend design is preferred