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NVIDIA

数字后端CAD工程师 ASIC PD Methodology Engineer

收藏职位
  • 我要分享
  • 30万-60万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,成长空间大,免费班车

发布时间: 2018-11-26发布

职位描述

What you'll be doing
Responsible for the development of timing analysis and closure methodologies and flow automation for large and high speed semicustom chips using deep submicron processes. This includes evaluating and helping improve commercial timing signoff tools, developing internal tools and solutions, and supporting the physical design implementation team to achieve speed of light timing closure.
 
What we need to see
•       BS in Electrical or Computer Engineering, MS preferred
•       3+ years of experience in physical design implementation of deep submicron digital ASIC.
•       Prior experience in synthesis, timing constraints, timing analysis and timing closure.
•       Power user of commercial STA tools such as Synopsys Prime Time or Cadence ETS
•       Solid knowledge about STA and timing signoff
•       Proficiency experience in Perl, TCL, Python or C++.
•       Good communication skills
•       Flow development or automation experience in ASIC backend design is preferred

职位发布者

Heather

HR

7天

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