Principal Analog Design Engineer (IP Group)
- 40万-55万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice,年底双薪,股票期权,成长空间大,技术领先
发布时间: 2018-10-11发布
职位描述
Position Description:
-Responsible for the design and development of analog/mixed signal SerDes/AFE/DDRIO macros from initial concept and specification, through final verification and conformance to customer requirements.
-Candidate’s background should include experience in high speed SerDes designs in low geometry CMOS processes and have a working knowledge of a set of common SerDes standards/AFE/DDRIO and their electrical requirements.
-The candidate must have deep design experience in one of more of the following SerDes circuit blocks: Driver; ADC/DAC; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators.
Position Requirements:
-Candidate must be able to own a block or set of blocks for analog SerDes/AFE/DDRIO IC design. -Cadence needs to be familar with the design process, required handoffs to the top level design team for smooth integration, and robust block verification.
-Candidate should have good problem solving skills, analog aptitude, communication skills, and the ability to work cooperatively in a team environment.
-Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and design experience at >6.25Gbps and in <40nm technologies are a plus).
- BSEE [MSEE preferred]
- Minimum 7 years experience in CMOS SerDes/AFE/DDRIO IC circuit design
职位发布者
cadence hr
Sr.Manager&BP
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,浦东嘉里城(7号线,花木路站)
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