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哎呀,这个职位已经下线啦
成都海光集成电路设计有限公司

Clock network design engineer

  • 30万-40万/年
  • 北京
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2018-10-26发布

职位描述

岗位职责:
1. Work with the SoC architecture team to define the top level clock structure of a server CPU scale SoC
2. Implement the top level clock with EDA tools and/or manual scripts
3. Perform circuit simulations and verifications to make sure the clock structure meets different specs, such as skew, latency, power, reliability
4. Working with different function teams to solve clock related issues

任职资格:
1. BS/MS/Ph.D. Degree in Electrical/Electronics Engineering
2. 7+ years of hands on experience in large scale hierarchical SoC physical design
3. Experienced with common EDA tools flow, ie: ICC2/Innovus/Prime Time/Calibre
4. Experience in transister level Spice simulation
5. Experience in top level clock implementation either in H-Tree or Mesh is a plus
6. Proficient in scripting with TCL, perl, shell
7. Good verbal and speaking English

职位发布者

孙晓琛

HR

7天

简历处理用时

95%

简历及时处理率