Front-end Senior Engineer – Verilog RTL Design

Role & Responsibilities:
-      Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
-      Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
 
Skills and Experience:
-      MS degree in Electrical Engineering, Mathematics, Computer Science, or equivalent education background, MS with more than 3-5 years or Bachelor with more than 5-8 years of industrial experience.
-      Familiar with Verilog RTL design and has experience of large digital ASIC project.
-      Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
-      Familiar with unix/linux and scripts (tcl, perl etc.)
-      Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager
-      Good English required both verbal and written