DFT Engineer

What you'll be doing:

• You'll be responsible for DFT planning, DFT implementation, DFT verification and silicon bring up at IP or fullchip level for all of NVIDIA's semiconductor products, starting with Memory BIST design and implementation.
• In addition, you will have chance to improve DFT design, architecture and flow continuously.

• BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or related domains.
• Solid background on Verilog and ASIC design
• Proven knowledge and expertise in defining and implementing 1500, Scan test plans and ATPG
• Deep understanding on Memory BIST
• Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
• Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
• Strong programming and scripting skills in Perl, Python or Tcl desired
• Excellent written and oral communication skills in English with the curiosity to work on rare challenges