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海光集成电路

CPU design senior engineer

收藏职位
  • 我要分享
  • 50万-80万/年
  • 北京
  • |
  • 5年以上
  • |
  • 硕士
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,年度旅游,技术领先,成长空间大

发布时间: 2019-02-01发布

职位描述


CPU top-level floorplan engineer
Key Qualifications
§  Indepth knowledge in hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and dealing with pad-ring logic/IP
§  We value your experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing.
§  Showcase your strong TCL/Perl/Makefile scripting knowledge and experience developing complex algorithms, managing, and regressing P&R flows.
§  Familiarity with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies is needed.
§  We are looking for a self-motivated, enthusiastic problem solver with strong interpersonal/communication skills are necessary.
§  ICC/ICC2 or Encounter knowledge is needed.
§  Technical leadership experience a plus.
 

职位发布者

孙晓琛

HR

7天

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