CPU design senior engineer
CPU top-level floorplan engineer
§ Indepth knowledge in hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and dealing with pad-ring logic/IP
§ We value your experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing.
§ Showcase your strong TCL/Perl/Makefile scripting knowledge and experience developing complex algorithms, managing, and regressing P&R flows.
§ Familiarity with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies is needed.
§ We are looking for a self-motivated, enthusiastic problem solver with strong interpersonal/communication skills are necessary.
§ ICC/ICC2 or Encounter knowledge is needed.
§ Technical leadership experience a plus.