CAD工程师

Interface with foundry to install, verify and maintain the PDK, standard cell lib from Fab
Generate script to help project team to switch the design across different process node
Support design team the usage for the design flow and methodology optimization. To improve the design efficiency.
Candidate’s background should demonstrate good problem solving skills, excellent analog aptitude, good communication skills, and ability to work cooperatively in a team environment.
Integrate the tape-out database including related technical documentation
Responsible for the final tape-out physical runset generating and verification (DRC/LVS/ERC etc)

Position Requirements:
Bachelor degree with 5+ years of applicable experience, Master degree with 3+ years of experience in electrical engineering, microelectronics.
Ability to work effectively alone or as well as in a team.
Essential that the individual demonstrates strong communication, verbal and written
Requires good communication skills in English.
Experience in ASIC flows and usage of related EDA tools
Excellent script languages skills for internal tool development, such as Perl, Tcl, Shell, Skill and Python

Desirable Qualifications:
Experience in Pcell development or P&R is a plus
Fab background is a plus
Solid understanding of IC design technology and process/methodology in IC design solutions
Familiar with Cadence analog and mixed-signal EDA tools is a plus
Self-motivated, able to work as a team player, excellent verbal and written communication skills in English.

If you have interest, PLS send your CV to yingc@cadence.com