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Synopsys

Verification (Formal tools) Application Engineer

  • 30万-40万/年
  • 北京
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间: 2019-08-02发布

职位描述

Synopsys is uniquely positioned to benefit from this shift and offer a broad RTL signoff platform that enables signification efficiencies in bringing SoC to market.

Spyglass is an important platform of Synopsys RTL SignOff solution that provides complete static analysis to ensure all aspects of the design are optimized before implementation such as Lint, CDC, Power, Constraints, DFT/DSM etc.


This position provides technical expertise, support, and guidance of formal verification tools and effective application of formal verification within client’s methodology and flows; Includes analysis of environment and setup, identification of appropriate blocks and metrics, analysis of tool performance and problem complexity, and optimizing modeling logic, formal testbenches and environment for optimal tool performance. May be involved in defining, scoping and implementing detailed customer verification requirements.
Will be the formal verification champion and provide training on concepts, methodology and tool usage. Application of formal methods including formal property verification, sequential equivalence checking, formal coverage analysis, connectivity checking and other formal verification apps.

Requirement:
- BS degree in CS/EE with 3+ years of experience as an ASIC engineer.
- Experience in developing RTL and verification environments for complex ASICs using Verilog, VHDL or SystemVerilog is required.
- Experience in CDC (clock domain checking) analysis, synthesis/timing analysis, Power verify and analysis, power estimation, etc.
- Possesses a solid understanding of Formal Verification concepts plus hands-on experience verifying and signing-off using formal verification.
Exercises independent judgment in selecting methods and techniques to obtain solutions.

职位发布者

HR

7天

简历处理用时

97%

简历及时处理率