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Synopsys

Verification AE _Lower Power solution

  • 30万-40万/年
  • 深圳
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间: 2019-04-04发布

职位描述

Advanced intent-driven low power design flows requires complete and rapid checking of low power implementation and behavior validity at every stage in the flow. Our product provides native low power simulation and advanced low power static verification solution to manage the increased low power verification complexity.

VC LP is a multi-voltage low power static rule checker that can help pipe-clean IEEE 1801 Unified Power Format(UPF) low power design intent, and validate that UPF low power design intent is accurately implemented and functions correctly.
- This position based in Shanghai, candidate will be responsible for successful deployment of Synopsys low power verification flow to a growing customer base in AsiaPacific.
- The responsibilities include onsite deployment of industry leading automation and verification technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement.
- Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex verification issues for customers cutting edge ASIC designs.

- Requirements:
- MS or PhD majored in EE with more than 5 years of IC design/verification experiences.
- Good knowledge of high-level design methodologies and strong communication skills are required. Ability to work with customers and R&D teams is important.
- Real project experiences in ASIC/SoC verification are required. Proficient with HDL (Verilog/VHDL), HVL(e/Vera/SystemVerilog), C/C++, Unix, and expert knowledge of low power verification(including LP static check and dynamic simulation, and UPF/CPF) is requested.

职位发布者

7天

简历处理用时

92%

简历及时处理率