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Synopsys

Interface IP Application Engineer

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  • 我要分享
  • 30万-40万/年
  • 深圳
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间: 2019-12-06发布

职位描述

Synopsys offers a broad portfolio of high-quality, silicon-proven IP solutions for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. This position will be responsible for technical support of customers using Synopsys DesignWare Cores IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. Responsibilities Include

-         Discussing with customer on their application and SoC design, Capturing and understanding their design requirements, Proposing DW IP solutions to best-fit customer requirements with competitive PPA 
-         Providing direct technical support and assistance to enable customers to use DW IP successfully
-         Working with the sales teams to manage the IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships 
-         Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across the business units and with other product line teams to provide high quality support for customers. 
-         Writing application notes, attend technical conferences and review projects and protocol specifications. 
-         Providing technical guidance and support to the sales team during calls, meetings, and marketing events. 
 
Requirements:
- Bachelors and/or Master’s Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.
-         Experience with one or more I/O protocols, such as Ethernet, USB, DDR, HBM2, PCIe, CCIX, MIPI, SATA, HDMI, Mobile Storage and Multi-protocol Serdes are preferred.
-         An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred. 
-         Minimum of 5 years relevant experience in ASIC/SoC front-end design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking.
-         Full understanding of digital design methodologies and tools including formal verification.
-         Ideally have experienced at least one ASIC/SoC tape-out from concept to full production.
-         Silicon debug and troubleshooting skills are highly desirable.
-         Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities.
-         Strong communication skills and ability to interact with customers as well as peers.
-         High degree of self-motivation and personal responsibility.
-         Strong analytical, reasoning and problem solving skills and attention to details

职位发布者

HR

HR

7天

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