IC verification Engineer

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30万-50万/年
成都
|
3年以上
|
硕士
|
全职

职位诱惑: 五险一金,福利好,技术领先,成长空间大,通讯津贴,交通补助,节日礼物,技能培训

发布时间: 2019-02-27发布

职位描述

JOB DESCRIPTION:
- Engaged in SOC/ASIC module-level and system verification
- Individually develop test plan and set up UVM verification environment
- Create constrained random and C pattern testcase
- Engaged in Gate-level simulation with SDF annotation and Low-power with UPF
- Participate in digital/analog mix-signal Co-simulation
- Develop/maintain/enhance environment/scripts/makefiles

QUALIFICATION:
- BSEE with minimum 3-year experience in SOC/MCU verification
- Proficiency in Systemverilog/ Verilog/C
- Solid knowledge on advanced verification methodology,UVM is preferred
- Good knowledge on ARM architecture,AMBA2.0 and AMBA3.0
- Experience on scripting language,Perl and shell are preferred
- Hands on experience with simulation and verification tools, such as VCS/NC
- Experience on DDR/USB/Serdes is plus
- Familiar with FPGA flow is preferred
- Strong teamwork and communication ability