Physical Design Intern(实习生)
• Work in physical design team for large scale ASIC chip physical implementation.
• Focus on physical design of deep sub-micron SOC chips for block level floor planning, timing closure, place&route, physical verification etc.
• The individual is expected to be accountable for block level project delivery.
• Familiar with ASIC backend design flow/methodology.
• Knowledgeable in deep submicron ASIC design.
• Strong problem solving skills, and attention to details
• Good interpersonal skills (verbal and written)
• Dedicated, hardworking and good team player
• Familiar with Unix/Linux environment and good at scripts
• Familiar with Back-End (physical design) EDA tools is a plus.
Bachelor of EE or CS. 4-5 days working per week.