IP Design Verification Engineer-PCIe

Job Responsibilities:

AMD NBIO (North Bridge IO) team delivers industry leading high performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP inside NBIO. The candidate will be working with the global team on PCIe IP verification
Responsibility:
* PCIe controller verification
* Work with architecture/IP designers to get a full deep insight on the design under test
* PCIe IP test bench build, verification component build

Education& Qualifications:

Candidate is preferred to be MSEE with minimum of 8 years, or BSEE with minimum of 10-year experience in digital ASIC/SOC design verification.

Experience:

1. Complex IP Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
2. Good knowledge of at least one verification methodology. UVM is preferred
3. Good knowledge of Verilog/C/C++/System C/SystemVerilog.
4. Verification insights into random techniques.
5. Experience of verification lead is an asset.
6. Experience of PCIe verification is an asset.
7. Experience in power verification is an asset.
8. Verification of Virtualization is an asset.
9. Good at both Oral English and written English
10. Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.