- 25万-50万/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,免费班车,交通补助,技术领先,成长空间大
发布时间: 2022-03-21发布
职位描述
Job Responsibilities:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:
- MS degree of EE.
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
- Familiar with unix/linux and scripts (tcl, perl etc.)
- Fluent English on talking, presentation and writing documents.
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
职位发布者
vicky cai
HR
7天
简历处理用时
100%
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