Campus Recruitment - Digital Designer
Candidates will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off. Candidates will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests.
• RTL implementation base on design specification;
• Setup and maintain frontend flow, e.g. Lint, CDC, LEC and Synthesis;
• Co-work with verification/validation team on design failure;
• Co-work with backend team on timing closures and P&R;
• Design document writing and maintain.
1.BS/MS in EE
2.Enrolled in the master's degree course related to ASIC development
3.Experience with digital design, running EDA tools of simulation and running frontend flow
4.Good communication skills and willing to learn