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百瑞互联

ASIC Design/Verification Engineer 设计验证工程师

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    ¥1k
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  • 25万-50万/年
  • 上海
  • |
  • 工作经验不限
  • |
  • 本科
  • |
  • 全职

职位诱惑: 股票期权,技术领先,成长空间大,五险一金,节日礼物,老板nice,福利好,年终奖金

发布时间: 2019-05-17发布

职位描述


Job Description
·        Analog and digital IP integration for SoC and verification
·        RTL handoff quality check using EDA tools
·        Prepare relevant SDC file
·        Prepare relevant UPF file
·        Co-work and Support ASIC implementation
·        Co-work and Support FPGA prototyping
·        Co-work and Support software and system productions
·        Write design documents
Qualifications
·        2+ years hands-on experience in ASIC RTL design. Experience in Bluetooth, Mobile Computing or IoT is a plus
·        ASIC design verification and implementation knowledge
·        Good knowledge to RTL QA tools (for example Spyglass)
·        Good knowledge to UPF and low power verification (for example VCLP and VCS-NLP)
·        English documents reading
·        Good programming in Perl/Python, TCL and Shell programming
·        Good team work and communication skills
Location
      Room 310, No.500, Bibo Road, Pudong, Shanghai
 

职位发布者

鲁冬梅

HR

7天

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100%

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