Design Verification Engineer
- 20万-35万/年
- 上海
- |
- 3年以上
- |
- 硕士
- |
- 全职
职位诱惑: 五险一金,老板nice,天天下午茶,技术领先,年度旅游,节日礼物,成长空间大
发布时间: 2019-11-14发布
职位描述
Design Verification Engineer
JOB DESCRIPTION:
· Create independently leading edge constrained-random verification environments and use them to drive functional correctness of innovative SoCs.
· Be responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques, such as Universal Verification Methodology (UVM).
· Design verification components such as bus functional models, monitors, and behavioral models.
· Implement functional coverage and assertions using System Verilog.
· Develop testing and functional coverage plans based on device specifications.
· Analyze and debug simulation failures, as well as functional coverage results.
JOB REQUIREMENT:
· Master’s degree in EE/CS;
· 3+ years in ASIC/SoC verification with UVM/SV environment.
· In-depth knowledge of verification flows, constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
· Experience is SSD controller is a big plus.