- 18万-30万/年
- 上海
- |
- 应届生/在校生
- |
- 本科
- |
- 全职
职位诱惑: 福利好,五险一金,技术领先,技能培训,成长空间大
发布时间: 2018-10-10发布
职位描述
Job Scope:
ASIC IP design and SoC integration
Job Responsibilities
- IP design based on C-model or design spec
- SoC integration and basic verification
- Support DV engineer to finish the IP level/full chip level verification (simulation, emulation and FPGA test)
- Work with Backend to drive full chip P&R and timing closure
Job Qualifications
- MSEE/MSCS Degree or equivalent
- Experienced in Verilog RTL coding and FPGA design
- Be good at C/C++ or perl/python
职位发布者
Maggie Ma
HR
7天
简历处理用时
100%
简历及时处理率
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