Application Engineer (SPB) 封装技术支持

1.Perform package design implementation, including floor planning, bump/ball map optimization with co-work between chip designer and PCB designer, considering the optimized package types, package substrate routing, power/ground planning, substrate layer, power/signal integrity performance and DFM closure. It also includes some supports for Cadence SPB tools.
2.The candidate will have the opportunity to work with Cadence IP team for some challenging designs, i.e. high performance DDR design; high speed SerDes design. The responsibility includes participating in IP package implementation scheme, i.e. suitable package type selection; bump pattern planning; package manufacture cost consideration; whole chip package design; package design optimization according to the power/signal integrity performance and DFM; methodology and flow development.

Position Requirements:       
1.  BS degree with 5~10+ years of applicable experience, MS degree with 4~8+ years of applicable experience in electrical engineering, microelectronics.
2.  Experienced with Package design flow, familiar with different package type manufacture process and methodologies, familiar with Cadence package design and PCB design tools.
3.  Solid knowledge on DDR and SerDes Design.
4.  Good communication and team work skills. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.