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Synopsys

Verification Engineer (for AI Product)

收藏职位
  • 我要分享
  • 30万-50万/年
  • 北京
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,技能培训,成长空间大

发布时间: 2018-12-14发布

职位描述

Job Title: AI Verification Engineer
Location: Shanghai / Beijing
 
Job Descriptions
1.       Work with architects, designers, to develop and execute verification of AI chips or SoCs.
2.       Define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals.
3.       Define overall verification strategies, methodologies, and simulation environment.
4.       Build verification environment using SV/UVM methodology. Build reusable functional models, monitors, checkers and scoreboards. Drive coverage driven verification closure
 
Minimum Requirements
1.       M.S. in Computer Science, Computer Engineering, or Electrical Engineering (or a closely related field of study).
2.       Typically requires a minimum of 4 years of related experience.
3.       Fluent in verification language such as UVM/OVM/RVM/System Verilog, Vera, Verilog
4.       Experience in writing Test-plans and creating directed and random testcases
5.       Strong scripting skills in Perl, Python, shell etc.
 
Preferred Qualifications
1.       Knowledge of machine learning, deep learning, and other AI algorithms
2.       Experience in AI accelerator or other hardware accelerator verification
3.       Strong written and verbal communication skills
 
 

职位发布者

7天

简历处理用时

94%

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