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Advanced Micro Devices

GFX FE Tile Owner

  • 28万-50万/年
  • 上海
  • |
  • 5年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,免费班车,交通补助,成长空间大,技术领先

发布时间: 2020-03-30发布

职位描述

RESPONSIBILITIES:
·        Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
·        Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
·        Work with Physical Design team on Floorplan, budgeting, timing closure, signal integrity, ECO flows, Power analysis, etc.
·        Resolve formality,  leda, CDC, connectivity and repeater issue.
·        Analyze gating efficiency report to improve RTL quality and optimize power.

REQUIREMENTS:
·        Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
·        Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC..
·        Some Physical Design exposure required.
·        Some exposure to DFT is a strong plus.
·        Expertise in script (Perl, Tcl) is a must.
·        Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
·        Must have good communication & Analytical thinking skills.

EDUCATION:
·        Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area
 

职位发布者

vicky cai

HR

7天

简历处理用时

97%

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