哎呀,这个职位已经下线啦
Cadence
资深模拟版图设计工程师
- 30万-42万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice,年底双薪,股票期权,成长空间大
发布时间: 2018-11-30发布
职位描述
Position Description:
- Skillful capable of AMS layout Design area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc.
- Proficient with Cadence layout tools specifically Virtuoso XL and Assura (Cadence 6.1 experience a plus)
- Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
- Fundamental understanding of IC design technology and process/methodology
- Skilled in Analog IC top level chip assembly including floorplanning and block layout
- Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
Position Requirements:
- BSEE degree with 7+ years of applicable experience in analog design industry.
- Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
- Requires good communication skills in English and Chinese.
职位发布者
cadence hr
Sr.Manager&BP
7天
简历处理用时
98%