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厦门御芯微

LSI junior engineer

收藏职位
  • 我要分享
  • 15万-30万/年
  • 厦门
  • |
  • 1-3年
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,股票期权,年度旅游,技术领先,成长空间大,技能培训

发布时间: 2019-02-26发布

职位描述

As a junior design/verification engineer in Defender Chip, you will work in a highly innovative and motivated environment. Supported by our customized SPARC Core, we can offer you a unique experience of designing/modification of CPU core on SOCs. In addition, you will be dedicated to security chip/TPM chip development and travel through many elements across information security and SOC designs.

Joining a fabless start up brings great oppotunities as well as challenges ahead. We appreciate those who could grow with us in the long run while providing variety of development paths and oppotunities of stock options.

Job responsibilities:

1. Fully understand design specs.
2. Learn and perform development activities, including RTL design, synthesis, Formal Verification, and Static Timing Analysis
3. Unit-level and System-level verification
4. Chip level integration
5. Provide support to senior engineers, simulate, analyze and debug current chip designs, include emulator and FPGA based HW and FW co-verification testing.

Qualifications:
1. Bachelor or Master's degree major in CS/EE/Math, preferable from a prominent university(985/211) and with good academic results.
2. Verilog RTL coding experience, including in-school projects.
3. Proficiency in English is a must.
4. Excellent analytical and debugging skills, ability to cooperate and working in a team.
5. Experience with design and verification flow preferred.
6. Synthesis, Simulation, Static Timing Analysis experiences preferred.

职位发布者

张先生

联合创始人/CEO/公司高管

7天

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100%

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