哎呀,这个职位已经下线啦
Cadence
资深数字前端设计工程师
- 37万-60万/年
- 上海
- |
- 3年以上
- |
- 硕士
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice,年底双薪,股票期权
发布时间: 2020-03-05发布
职位描述
Position Description:
- Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
- Proficiency in logic design, simulation
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design
- At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
- Essential Qualifications: Must have BS degree with 6~10+ years of applicable experience, MS degree with 3~7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
- Essential that the individual demonstrates strong communication, verbal and written.
- Requires good communication skills in English.
- Will have demonstrated successful completion of 10+ design projects as an individual contributor
- Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience
职位发布者
cadence hr
Sr.Manager&BP
7天
简历处理用时
97%
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海,浦东嘉里城(7号线,花木路站)
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